This invention relates generally to the design automation of Very Large Scale Integrated (VLSI) circuits, and more particularly to determining the effect of noise in digital integrated circuits.
As complementary metal-oxide-semiconductor (CMOS) technology scales down and moves toward deep submicron technologies, the effect of noise in digital circuits becomes critical. Noise can impact the timing results of a circuit and thereby can introduce functional as well as timing failures. For instance, if a noise glitch propagates to the input pin of a dynamic node or a storage circuit such as a latch, it can alter the state of the overall digital circuit and introduce functional error.
In electrical circuits, noise is an extraneous signal that can be generated from capacitively/inductively coupled nets in a digital integrated circuit. An example of a net is a logic signal wire that connects two or more electronic circuit components such as logic gates. One form of noise is crosstalk, which is a signal pickup from a changing voltage on another net. Another form of noise is propagation noise which is the glitch propagated from the input of a victim driver to its output. Propagation noise may combine with the crosstalk noise on the driver output net and further propagate through all the fanout gates. In the design of electric circuits, such as VLSI design, it is important to verify that the noise, which may be induced on a victim net of the chip by its neighboring aggressor nets does not affect the functionality or performance of the circuit.
Typically, noise analysis is used to determine the effect that noise glitches emanating from a victim net will have on a digital circuit. A noisy waveform propagation analysis, which is one type of noise analysis that seeks to understand the effect that propagation noise will have on timing of a victim net, is important in evaluating results from a timing analysis of the circuit. Straightforward techniques that have been used to analyze the effect of propagation noise include a point-based technique, least square error based technique, weighted least square based technique and energy based technique. Generally, all of these techniques approximate the noisy waveform associated with the propagation noise with an effective ramp waveform and then propagate the ramp waveform from the input of a logic gate to the output of a logic gate to determine the effect that the noise has on the delay and slew of the gate. None of these techniques are accurate because the noisy waveform cannot accurately be approximated by an effective ramp waveform. As a result, these techniques may introduce unjustified pessimism during timing analysis of the digital circuit. To avoid the issues associated with approximating the propagation noise with an effective ramp, most glitch propagation analysis techniques require special pre-characterization of the logic gates in the digital circuit. The need to pre-characterize for many combinations of logic gate environments greatly complicates the design flow of a digital circuit and imposes additional burden on the already heavy library characterization effort used by digital circuit designers.